1. Field of the Invention
The present invention relates to a double-gate semiconductor device having a top gate electrode and back gate electrode, and a method of fabricating the same.
2. Description of the Related Art
Recently, the performance of an LSI formed on a silicon substrate has been significantly improved by miniaturization of device dimensions used in the LSI. This is so because the gate length is decreased or the thickness of a gate insulating film is decreased on the basis of a so-called scaling law in a MOSFET used in a logic circuit or in a storage device such as an SRAM. Presently, to improve the cutoff characteristic of the MOSFET, a transistor called a double-gate MOSFET in which a gate region is additionally formed on the substrate side of the conventional planar MOSFET is proposed as one type of a MIS semiconductor device having a three-dimensional structure, and an attempt to improve the current characteristics of this double-gate MOSFET is already reported (e.g., S. Harrison et al., IEDM 2003, 18.6, pp. 449-452 (2003), K. W. Guarini et al., IEDM 2001, 19.2, pp. 425-428 (2001), U.S. Pat. No. 5,773,331).
Unfortunately, the double-gate MOSFET, particularly, the planar double-gate MOSFET is very difficult to fabricate, and it is also difficult to obtain desired device characteristics. Root causes of this problem are that it is difficult to form the top gate electrode and back gate electrode in self-alignment with each other, and it is also difficult to make the gate lengths of the top gate electrode and back gate electrode equal to each other.
In the planar double-gate MOSFET by S. Harrison et al., for example, a technique called SON (Silicon On Nothing) is used to form an air gap immediately below the channel region, and then form the gate insulators and the gate electrodes (see FIG. 1 of S. Harrison et al.) In this method, however, it is difficult to use a mask process when the back gate electrode is processed. Since the air gap is filled with the material as the back gate electrode, the gate length of the back gate electrode is much larger than that of the top gate electrode (see FIG. 5 of S. Harrison et al.) This large (length) back gate electrode increases the overlap region of the back gate electrode and a source/drain region, therefore, a parasitic gate overlap capacitance Cov in this portion much increases. Consequently, the DC characteristics may improve by the backgate control, but the speed of an AC operation would be decreased. (see FIGS. 14 and 15 of S. Harrison et al.) The planar double-gate MOSFET by K. W. Guarini et al. is also called a PAGODA which is obtained by forming a double-gate MOSFET structure by separately forming a top gate electrode and back gate electrode, and bonding these electrodes (see FIG. 1 of K. W. Guarini et al.) Since the bonding technique is used, channel portions except for the gate electrodes can be laid out without major constraint, and a separate gate structure is also available (applicable) (see FIG. 1C of K. W. Guarini et al.) However, the fabrication process is very complicated. In particular, the thickness of the Si channel region is decreased by using CMP (Chemical Mechanical Polish) or the combination of Si oxidation and SiO2 removal many times, so thickness variations between the device patterns are expected to be large. These variations are directly related to (or concerned with) the variations in threshold voltage.